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Based on the original ANSI/VITA 17.0 Front Panel
Data Port standard for a parallel data cable connection, Serial FPDP
(ANSI/VITA 17.1) is a high performance data link that provides low
latency, bi-directional data flow with broadcast capabilities for
real time capture of raw data in sensor signal processing
applications.
Most protocols for high speed cable interconnects are not designed
for real time, streaming data applications. Instead, most
interconnect protocols target large networking and communications
infrastructure. This generally requires the protocol to limit packet
size, perform complex negotiations when establishing
source/destination connections, and adhere to high level arbitration
and prioritization mechanisms. Often combined with backwards
compatibility requirements, this results in the protocol having
several complex networking layers of overhead that are not only
unnecessary for real time applications, but unacceptable in terms of
performance.
Alternatively, Serial FPDP is primarily hardware based and optimized
for large data transfers, minimal CPU utilization, and low latency,
deterministic applications. These characteristics have lead to its
wide spread popularity for C4ISR (command, control, communications,
computers, intelligence, surveillance, and reconnaissance)
deployments including:
Synthetic Aperture and Phased Array Radar
Signal Intelligence (SIGINT, COMINT, and ELINT)
Sonar
Other target applications include medical,
semiconductor, and seismic imaging.
FPDP
Supporting transfers of 160 MB/s, FPDP has provided
a strong solution for streaming sensor data from A/D converters to
signal processors because of its lightweight, low overhead protocol. This simple FPDP protocol is accompanied by a relatively simple
hardware interface.
With a 32-bit parallel synchronous bus, transfer
rates are determined by the clock frequency of a single master
device as the protocol does not include address or arbitration
cycles. Using differential PECL strobe signals to eliminate
glitches, SYNC signals are repeated at the end of every frame of
data to assure channel synchronization is maintained in every frame. DIR (Data Direction), DVALID (Data Valid) and SYNC (Sync Pulse)
signals are issued at data transmission and NRDY (Not Ready) and SUSPEND
(Suspend Data) are issued as receive operations. Other
signals are provided for
Data, PIO1/PIO2 (Programmable I/O), and
Clock (Data Strobe).
Parallel Cable
FPDP’s limiting factor is the physical 80-conductor
parallel ribbon cable utilized to
transport data. Maximum distances
of a few meters essentially limit FPDP to
board-to-board connections within a given chassis, or in some instances
chassis-to-chassis
connections within the same rack mount enclosure. Parallel ribbon
cables do not have optimum resiliency in terms of EMI or withstanding exposure to external elements required by many target
systems. This can present an obstacle to deployment given these
system requirements for high availability, Mean-Time-To-Failure, and
life cycle maintenance.
Serial FPDP
Supporting point-to-point, broadcast chaining, and
single or multiple master
ring topologies, Serial FPDP is rapidly
becoming the interconnect of choice for
streaming sensor signal
processing systems. By serializing FPDP data streams, it supports
connections of up to 10 kilometers, providing the ability to place
great distances between processing elements and sensor subsystems.
On the transmit side, parallel FPDP data is
converted to Serial FPDP. On the receive side, Serial FPDP data is
converted to parallel FPDP. The first step of this transmission and
conversion process involves input FPDP data made up of 32-bit words
that pass through a transmit FIFO to an 8B/10B encoder, with data
then serialized, and sent over a fiber or copper wire. On the
receive side, data is deserialized, then decoded, and sent to
receive FIFO’s before being provided as FPDP output data.
Serial FPDP utilizes the Fibre Channel link layer
protocol for data transport. Using a subset of the link layer’s
8G/10B encoding scheme, ordered sets are modified for Serial FPDP
protocol but commercially available Fibre Channel IC’s can be
utilized to interface to the physical media.
In addition to transmitting standard FPDP 32-bit
data words, Serial FPDP also transmits FPDP control signals. The
protocol supports flow control and three primary types of frames:
data frame, SYNC frame, and SYNC without data frame. With variable
size frames consisting of up to 512, 32-bit words per frame, Serial FPDP data overhead is less than 2%. In a 512, 32-bit word frame,
only six words are allocated to overhead.
Micro Memory believes the dramatic growth in market
share for Serial FPDP is likely to continue. With its lightweight
protocol, ease of use, and roadmap that includes support for 10Gb
links, it is possible that Serial FPDP will become the defacto
standard interconnect for streaming sensor signal processing.
MM-6137FC
Specifically designed for use on Micro Memory’s
line of Othello VME carriers, the MM-6137FC provides two completely
independent 2.5Gb Serial FPDP links on a single PMC card. The
architecture enables individual streams to run simultaneously in any
direction without the obstruction of a PCI-to-PCI bridge between the
links and the on-board Othello PCI memory nodes.
Serial FPDP on Othello VME carriers
Configured with two MM-6137FC PMC’s, Micro Memory
currently offers four Serial FPDP channels on its Othello VME
carrier boards with optional connectivity to switch fabrics such as
Serial RapidIO, RACE++, and StarFabric.
The pre-integrated solutions provide four
independent 2.5Gb Serial FPDP links that can each operate
concurrently, at the full bandwidth of 247 MB/s, in any direction.
Acting as a front end FIFO, this implementation provides the ability
to acquire streaming sensor data at almost 1,000 MB/s and rate
buffer it in the up to 8GB of on-board SDRAM. Data can then be DMA’d
to downstream DSP nodes on the switch fabric backplane.
On the MM-15x0 and MM-16x0, incoming data can
also be pre-processed in the CoSine
Xilinx® V-4™ FPGAs, performing functions such as FFTs,
FIR filters, convolution and demodulation before transmitting data
onto conventional downstream DSP nodes for decision based,
floating-point operations.
MM-15x0 Combined with
two MM-6137FC PMCs, the MM-15x0 provides four 2.5Gb
Serial FPDP channels with V4 SX55/LX160 FPGAs on a VxS
VITA 41 form factor with two
Serial RapidIO x4 ports on P0.
MM-16x0 Combined with
two MM-6137FC PMCs, the MM-16x0 provides four 2.5Gb
Serial FPDP channels with V4 SX55/LX160 FPGAs on a
VITA 46 form factor
with four Serial RapidIO x4 ports on the MGT backplane connector.
MM-6467D Provides four
2.5Gb Serial FPDP channels and up to 8GB of SDRAM on a VME64 form
factor with two RACE++ ports on P2.
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