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RapidIO Interconnect
RapidIO®
is a packet‑switched interconnect targeted toward distributed‑memory
systems and subsystems.
RapidIO has
distinct advantages over alternative architectures for distributed
multiprocessor systems. Instead of a hierarchal, spanning tree
topology, such as found with PCI-X, PCI-Express, and Advanced
Switching, RapidIO supports peer to peer communications with
dual-star, mesh, daisy-chained or tree topologies.
Other
architectures, such as PCI, are based on the assumption of a central
host and a common memory map shared among all devices. But many
embedded systems have multiple distributed processors that can
benefit greatly from having direct access to multiple different
endpoints (I/O, memory controllers, or other processing elements).
RapidIO
enables highly efficient data transfers in part through its
provisions that enable multiple devices to share memory globally.
RapidIO and its hardware-based message passing architecture were
specifically designed for these types of distributed systems, thus
enabling higher performance and reduced complexity for embedded
applications.
The necessity to bridge PCI and RapidIO
Because
the commercial server markets drive the design and production of
many high performance I/O peripherals (fibre channel, Gigabit
Ethernet, Infiniband, etc.), providers of I/O silicon overwhelmingly
choose PCI/PCI-X/PCI-Express as the digital interface for their
chipsets. These various server markets also facilitate a large
breadth of options for I/O connectivity (graphics, video, firewire,
USB, etc.) and long distance interfaces to larger network
infrastructures, e.g. ATM to WAN.
The embedded
systems market has historically not had the volume demand necessary
to drive these high performance I/O silicon vendors to offer devices
for architectures other than what would be found in mass market
servers. Despite RapidIO’s many technical advantages, it is
unlikely that it will be able to change this tradition.
However, for
embedded system designers, availing of the latest I/O peripherals
and other related silicon produced for high end commercial servers
has and will continue to be a definitive requirement. It provides
the ability to leverage mass economies of scale, access to mature
software and device drivers, and a means of utilizing cutting edge
technology for various I/O functionalities.
ASIC-based Bus Translation Bridges
Balancing this need for an interconnect with a truly distributed
architecture, that can be found in RapidIO, with the requirement to
interface to server I/O peripherals, based on PCI, generally
requires embedded system designers to implement ASIC-based
translation bridges. In this case, it would involve an ASIC bridge
that has a PCI endpoint and a Serial RapidIO endpoint, with the
bridge translating the PCI protocol (PCI, PCI-X, or PCI-Express) to
RapidIO. While providing essential functionality, these bridges
have several performance drawbacks.
Regardless of
fine tuning adjustable parameters, bus translation bridges will
inevitably force retires and disconnects. Combined with limited
FIFO’s and inefficient pre-fetching, this will result in performance
penalties in terms of latency and throughput that can negatively
impact the greater system.
Alternatively, Micro Memory offers its CoSine™ FPGA on
several current and forthcoming board-level form factors as an
effective alternative to bridging between PCI-X and Serial RapidIO.
CoSine maximizes bandwidth and
minimizes latencies for transfers between PCI/PCI-X/PCI-Express to
Serial RapidIO through the implementation of its multi-ported DDR
controller. Multi-ported memory controllers are the highest
performance solution for transferring data between different bus
protocols in real time. This provides seamless, transparent access
between PCI and Serial RapidIO endpoints residing on different bus
topologies without the performance penalties experienced when
utilizing bus translation bridges.
In addition,
as a true System-on-Chip, CoSine provides two embedded PowerPC’s,
each with their own separate, dedicated DDR memory controllers,
programmable Flash, and a shared Ethernet connection enabling them
to each operate as fully functional computers. CoSine also includes
optional FPGA processing capabilities via its UPL block, especially
applicable to custom state machines for fixed point operations.
RapidIO on CoSine
The
Serial RapidIO interface on CoSine uses four full‑duplex
3.125 Gb/sec lines operating in parallel. Full duplex operation is
achieved by using separate differential transmit and differential
receive pins and traces. The Serial RapidIO physical and protocol
layers use 10 bits to transmit 8 bits of information and a packet
size of 276 bytes to transmit 256 bytes of data. The remainder of
this maximum sized packet is used, similarly to Ethernet, to
identify the sender, recipient, CRCs, and protocol information.
This results in a maximum data rate of 1.16 GB/sec simultaneously in
each direction. The RapidIO protocol includes error recovery
mechanisms for packet retry, stomp, link request/response, and CRC.
RapidIO is rapidly being adopted by leading
suppliers of embedded silicon semiconductor devices, such as
Motorola Freescale®, TI®, and Tundra Semiconductor®, along with
being sponsored by global OEM’s such as Ercisson®, Alcatel®,
Lucent®, and EMC® corporation.
Micro Memory
is a sponsoring member of the RapidIO Trade Organization.
RapidIO on Micro Memory Products:
Othello™ VME
carriers
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