EDA Environment

Tools & Resources

CoSine Links

CoSine Overview

Xilinx V-4 Famiily Overview

CoSine & CoSine Companion
Device Configuration

CoSine Development Suite &
Board Station

CoSine Approach to EDA
Design Flow

CoSine In-Chip Debugging

CoSine Secure Documents

CoSine Product Overview

CoSine White Papers

CoSine Detailed Device
Description

Utilizing CoSine in Synthetic
Apeture Radar

Utilizing CoSine's Corner
Turining DMA Engine for
Matrix Transposition

Memory Corner

EDA Environment

The guiding concept behind CoSine is to provide users with the most comprehensive FPGA infrastructure and powerful SoC architecture in a preconfigured solution to achieve the shortest possible development cycles.

This philosophy extends to the EDA (Electronic Design Automation) environment, where leading industry standard tool sets are utilized to rapidly develop application specific logic in CoSine’s UPL block.

Some of the most complicated facets of large FPGA designs are centered around fitting within clock limitations and closing timing. Balancing tight setup and hold times with corresponding propagation delays can be especially challenging in higher speed designs. But with the exception of the UPL block, and the associated UPL DMA, the CoSine netlist is supplied with a predefined clocking strategy and area and timing constraints to meet timing consistently. This strategy gives the flexibility and freedom to program custom, application specific logic in the UPL block without spending several weeks, or even months, writing and refining area and timing constraints to meet resource utilization requirements for other elements of the device.

Because of this approach, CoSine does not require tools or design flows specific to Micro Memory. Instead, CoSine utilizes industry proven, reliable and widely accepted design methodologies and tool sets from leading EDA giants such as Mentor (Modelsim and Leonardo Spectrum™), Synplicity® (SynplifyPro®), and Xilinx (ISE™ and XST™). It also supports the ability to utilize higher level abstraction tools from The MathWorks, Synplicity, Celoxica® and other Xilinx compatible EDA providers. This strategy avoids risking projects to design flow methodologies from board-level companies who are inherently not EDA vendors.

CoSine Design Flow

CoSine follows the industry’s standard EDA design flow for FPGAs: i. design entry, ii. synthesis, iii. simulation (behavioral), and iv. place & route, possibly followed by another iteration of simulation (timing). With CoSine, the only difference is that the CoSine netlist (supplied in the Development Suite) and constraint files be combined with the custom UPL netlist which results from the developer’s synthesis stage, prior to performing place & route.