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CoSine-on-Othello is offered on either VxS VITA
41 or VPX VITA 46 formats (see
VITA 41 versus
VITA 46) with complete Serial
RapidIO backplane connectivity. Serial
RapidIO is the backplane fabric
of choice for embedded systems due to its full
duplex serial switch fabric capabilities, low
latency and power requirements, and support for
distributed memory mapping. In addition to
Serial RapidIO, CoSine-on-Othello backplane
support includes a VME 2eSST interface and
certain options for the
Aurora serial link protocol.
Powered by two instances of the CoSine
System-on-Chip (SoC), these Othello VME boards
provide unprecedented memory bandwidth of over
40 GB/s and total aggregate internal throughput
of almost 60 GB/s. They are also the first VME
products to offer the application specialized
Xilinx V-4 SX and V-4 LX series of FPGAs.
FPGA based digital signal processing is
particularly relevant to streaming data
applications because it provides the ability to
perform multiple functions in parallel that
would otherwise be executed in a serial mode on
a conventional DSP or general purpose embedded
processor (Altivec® PowerPC, TI® C6xTM,
etc). Algorithms for fixed point functions such
as FFTs, FIR & IIR filters, data convolution,
reduction and digital down conversion are often
well suited to readily take advantage of
internal FPGA resources such as
multiply/accumulators, RAM, FIFOs and look up
tables.
By offloading these computationally intensive
functions from conventional processors, FPGA
based products such as CoSine-on-Othello can
increase overall system performance while
reducing total board count, total power
consumption, system cost and complexity.
Application Optimized Architectures
More important than raw bandwidth or FPGA
computing resources are the architectures found
in the CoSine-on-Othello series. The boards are
designed to support continuous data streams
through independent, non-blocking pathways.
Each of the mezzanine sites, four embedded
PowerPC processors, fourteen memory arrays and
FPGA processing resources are strategically
placed for optimum performance and combined with
an on-board crossbar that provides full
point-to-point, serial switch fabric
connectivity.
The CoSine SoC provides transparent access
between an interface to the mezzanine site and a
separate interface to the backplane or crossbar
switch, bridging two distinct ports each with
different bus topologies. Embedded systems
often require bridging between PCI/PCI-X based
devices and high speed serial or distributed
backplane fabrics such as RapidIO. ASIC-based
bus translation bridges are typically utilized
for these requirements but are inherently flawed
due to limited FIFOs, bridge disconnect/retries,
and inefficient pre-fetching. This can result
in latency or throughput penalties that prevent
reaching a “flow-through” mode critical to
streaming data applications.
Alternatively, CoSine utilizes a multi-ported
DDR controller for seamless bus translation that
provides near maximum theoretical bandwidth
without disconnects and retries. FPGA
processing resources are located in the heart of
the bridge with non-contentious access to the
interface ports and multi-ported DDR controller
for continuous reduction or convolution of high
speed data streams.
Flexibility
FPGA processing solutions generally reside in
the front end of an embedded system close to
input I/O such as A/D converters or fibre links
such as
Serial FPDP. In addition to
reducing board slot count, utilizing mezzanines
for this type of input functionality provides
the best solution in terms of product breadth
and selection, flexibility, reuse, technology
refresh, and often in performance as input
channels can be tightly coupled to FPGA
processing resources.
In terms of reuse, mezzanine sites enable OEMs
and defense primes to leverage a core processing
unit across multiple programs where processing
functionality is equivalent but input I/O
requirements tend to be system specific.
Each CoSine-on-Othello carrier includes two high
speed mezzanine sites with support for PMCs or
XMCs. Configured for PMC support, each PCI bus
can operate in conventional PCI mode at up to
66MHz or PCI-X mode at up to 133MHz. Configured
for XMCs, each site can support Aurora or Serial
RapidIO x4. Each site has a dedicated
pathway directly to FPGA processing resources
that is unobstructed by bus translation bridges.
Integrated Solutions
Any generally available PMC or XMC can be
integrated by Micro Memory into the
CoSine-on-Othello base carriers, with device
drivers built into the CoSine BSPs and specific
function calls reflected in associated APIs.
Pre-configured options include versions with
Serial FPDP, fibre channel, Gigabit Ethernet
TCP/IP off-load engines, and multi-channel A/D
converters.
Rapid Development Time
In addition to optimized architectures,
performance, and flexibility, CoSine-on-Othello
offers the shortest possible FPGA development
cycles. With its completely preconfigured FPGA
infrastructure, users can focus on developing
their application specific logic without
concerning themselves with coding other modules,
complicated SoC integration, or verification.
Ruggedized and Extended Temperature Models
Each of the CoSine-on-Othello boards was
specifically designed from the outset for
deployment in environments that undergo severe
shock and vibration with operation under extreme
temperatures. Extensive thermal modeling
analysis was performed over multiple CFD
iterations throughout the design process,
including prior to and post component placement,
and prior to and post actual board routing to
achieve optimal heat dissipation and cooling.
The rugged, extended temperature air cooled “DR”
models have operating temperatures of -40C to
+71C and the rugged, conduction cooled “DT”
models have operating temperatures of -40C to
+85C.
Domain Optimized Platforms
Different CoSine-on-Othello models specifically
address requirements for DSP intensive applications
(MM-1500, MM-1600) or logic intensive
applications (MM-1550, MM-1650). |
