CoSine^™ Development Kit & Board Station
Designed with the goal of customer success and ease of use, the CoSine Development Kit and Board Station are offered to facilitate the development process of application specific logic in CoSine’s UPL block and embedded software on each of CoSine’s PowerPC processors.

By supplying a fully preconfigured and functionally tested System-On-Chip (SoC), designers have the opportunity to complete the development and integration of custom logic and software in a complex SoC design faster than any other alternative approach.

Micro Memory Application Engineering support is included in the purchase of the CoSine development kit to assist in these design efforts, but it is expected that logic developers are experienced in programming VHDL and utilizing associated EDA tools.  It is also expected that software developers are experienced with Windriver’s® VxWorks® embedded operating system.  If this is not the case, Micro Memory’s Design Services are available to assist customers in one or both areas as necessary.

The CoSine Development Kit and Board Station include the following:

Hardware:

CoSine Board Station
The CoSine Development Kit includes a Board Station with a MM-333D ATCA board and Hardware Manual, standalone power supply, plastic mounting case, and various cables.

While production CoSine-based boards (MM-1300D, MM1400D) utilize the Xilinx Virtex-4 FX140, the MM-333D ATCA® CoSine development board currently utilizes a Xilinx Virtex-II Pro 2VP70 FPGA.  The MM-333D can operate in a standalone motherboard mode or within a Serial RapidIO ATCA chassis.  The board has a 64-bit/133MHz PCI-X PrPMC mezzanine site and a second XMC mezzanine site that supports Serial RapidIO (sRIO), PCI-X or PCI-Express.  Each of these two mezzanine sites connects to a separate and distinct port on the CoSine FPGA, and CoSine is capable of running both ports simultaneously.  In addition, a second set of SerDes are routed from CoSine to the ATCA backplane connector providing an alternative path to the Serial RapidIO x4 port on CoSine.  This alternative path requires a different CoSine bitstream that utilizes different CoSine MGT Rocket I/O pins.  CoSine is configured on the MM-333D as follows:

	64-bit/133MHz PCI-X interface from CoSine to PrPMC Site 1
	Serial RapidIO x4 interface from Cosine to XMC Site 2 or ATCA backplane connector, via 3.125GHz LVDS signals
	256MB to 8GB of 133MHz DDR SDRAM memory interfacing to CoSine’s primary, multi-ported memory controller and ECC engine
	32MB QDR II SRAM interfacing to CoSine’s UPL block
	128MB local DDR for each embedded IBM 405GP PowerPC™ processor
	Platform Flash for CoSine “on-the-fly” Reconfigurable Processing
	32MB programmable Flash for each of the two PowerPC’s and various boot images
	Fully operational 10/100 Ethernet port for easy download of files to the PowerPC processors
	RS-232 UART console for PCI-X PowerPC
	RS-232 UART console for Serial RapidIO PowerPC
	Connector to PCI-X PowerPC JTAG Debug port
	Connector to Serial RapidIO PowerPC JTAG port
	Mictor connector to PCI-X PowerPC for Windriver® Trace™ Debugger
	Mictor connector to Serial RapidIO PowerPC for Windriver Trace Debugger
	JTAG bitstream connector for Xilinx® ChipScope™ Pro

 

With each memory array fully populated (8GB for Primary Multi-Port DDR Array), the MM-333D has the following estimated power requirements:

Measurements may vary, and should only be used as an estimated guideline.  These values were calculated excluding any PMC or XMC mezzanine cards.

MM-333D Hardware Manual
A detailed Hardware Manual accompanies the MM-333D that documents interface specifications and electrical connections.

Power Supply
A standard 350 Watt ATX power supply with power switch for operating the MM-333D in standalone mode (as opposed to using the MM-333D in an ATCA chassis).

Mounting Case
Plastic standalone case for the MM-333D board and ATX power supply (as shown in photograph).

Cables
The following cables are supplied by Micro Memory in the CoSine Development Kit and Board Station:

	Bitstream Adapter Cable - used to interface the Xilinx Parallel IV Programmer programming cable to the MM-333D JTAG port. Quantity 1.
	Flying Lead” Parallel Cable – used to connect the MM-333D’s JTAG interface for CoSine’s PowerPC’s to the Xilinx Parallel IV Programmer. Quantity 1.
	Serial Console Cables – used to connect CoSine RS-232 ports on the MM-333D to a PC console. Quantity 2.

Logic:

CoSine Bitstream
Micro Memory supplies a fully preconfigured bitstream for the CoSine System-on-Chip.  All logic is completely integrated and fully functional.  Excluding the UPL block, QDR controller, and associated UPL interfaces there should be no need to modify other CoSine modules, internal buses, or related glue logic.  Micro Memory Application Engineers are available if it is determined that this type of modification is required.

Fixed Timing Constraints
One of the more challenging and time consuming aspects of FPGA development involves timing analysis.  This requires the performance capabilities of the FPGA device be well matched against the requirements of the design.  It also requires the principal developer to account for intelligent floor planning and resource utilization in advance of commencing the logical block implementation.

Providing user’s the power of a true System-On-Chip, along with a platform that gives them the ability to focus on their application specific logic has been a key consideration in CoSine’s architecture and development.  Towards this end, with the exception of the UPL block and its associated QDR controller and local DMA engine, the CoSine bitstream is supplied with isolated clock domains and fixed timing constraints.  This strategy gives the flexibility and freedom to program custom, application specific logic in the UPL block but not spend several weeks balancing timing constraints and resource utilization for other elements of the device.

The UPL has several fixed, predefined interfaces to the rest of the CoSine device which are defined in the VHDL wrapper file.  Outside of the UPL related blocks, the timing of the rest of the device has been pre-established by area and location constraints for critical portions based on the reference 1024 FFT UPL block.  Extensive floor planning has been used to maximize overall utilization of the FPGA, and ensure that timing is maintained when new custom logic is introduced into the UPL.  After integration is complete, the user is then responsible for ensuring that the UPL block and associated elements meet system timing requirements as established by the CoSine user constraint file (.ucf file).

In the normal design flow, the user will synthesize the UPL, followed by simulating it and correcting any problems that arise.  He will then integrate the resulting EDIF or NGC file with the original CoSine bitstream.  Several log files will be generated and should then be reviewed for errors.

VHDL UPL Wrapper
The VHDL wrapper includes code for the UPL block’s various interfaces, including the QDR II SRAM memory controller, UPL DMA engine, and other multiple points of high speed access.  Other glue logic for FIFO’s and internal block RAM is provided as part of 1024 FFT demo program.

VHDL Test Benches
A robust suite of VHDL test benches are provided in source form for user simulation.

Developer’s Manual
One of the most important tools Micro Memory provides CoSine developers to ensure project success and the fastest development cycle possible is thorough documentation.  For the UPL block, this includes a Developer’s Manual documenting all related interfaces to the UPL and its associated VHDL wrapper.  The kit also includes a demo program that runs a pre-installed off-the-shelf Xilinx 1024 Radix-4 FFT core in the UPL block.

The primary focus of the Developer’s Manual is centered around descriptions of the UPL VHDL wrapper and information required to develop VHDL in the UPL block.

It describes all interfaces from the UPL block to the rest of the CoSine FPGA bitstream and the QDR II SRAM memory controller.  It illustrates different UPL resource usages and implementations, such as with regards FIFO’s and memory‑mapped accesses.

Also included are descriptions of DMA operations that pipe data through the UPL block and illustrations of how signals are used for data transfer.  Software interfaces are documented on how the embedded PowerPC’s can be used to initialize, command, and control the UPL.

Demo Program
The UPL block is intended for customer application specific logic, but to demonstrate CoSine’s capabilities and the UPL block’s functional interfaces a demo program is provided that implements an off-the-shelf Xilinx 1024 Radix-4 streaming FFT as an example application.

This program demonstrates full system capabilities, including configuration and control by the PowerPC with DMA transfers from external interfaces.  The QDR II SRAM memory, internal Block RAMs, FIFO’s, and multiplexed accesses are also utilized to buffer the 1024 FFT data.

Embedded Software:

Board Support Packages

A Board Support Package (BSP) for Windriver’s Tornado® VxWorks 5.5 operating system running on the CoSine PCI-X IBM 405 PowerPC processor. A separate BSP is included for running on the CoSine Serial RapdIO IBM 405 PowerPC processor. Each BSP is accompanied by a Programmer’s Guide with documented API’s and example code.

Diagnostic Suites
Suite of standalone diagnostic test code (BIST) for running on CoSine PowerPC’s and exercising various internal functionality.  Also exercises peripherals and devices on PCI-X and Serial Rapid IO.

Suite of diagnostic C test code for running on external PCI-X PowerPC processor (PrPMC Site 1).

Suite of diagnostic C test code for running on external Serial RapidIO^® PowerPC processor (XMC Site or ATCA RapidIO endpoint).

CoSine links:

Overview

Applications

Device Interfaces

CoSine on Othello™ VxS VITA 41 and VITA 46/48