Overview
CoSine™ is a highly integrated, completely preconfigured System-on-Chip (SoC) for real time FPGA
based signal processing. Bridging two high speed interfaces (Serial RapidIO®, PCI-X™, or PCI-Express™)  through a multi-port DDR controller, the elegant design enables non-contentious access to a User Programmable Logic (UPL) block.

Similar to a structured ASIC, the IP cores, memory controllers, specialized DMA engines, embedded processors and surrounding logic are factory preconfigured and supplied as a fully tested system. This provides users the ability to focus on application specific state machine processing in the UPL block without concerning themselves with coding other modules, complicated SoC integration, or verification.

By providing a fully functional and verified solution, developer’s are given the opportunity to complete their custom logic and software in a complex SoC design faster than any other alternative approach. Supplying a proven design has the added benefit of greatly reducing the “multiple-variable” problem that can be so challenging for designers during the system debug process.

CoSine not only combines the functionality of several chips into a single device. With a focus towards processing real time data streams, CoSine’s elegant architecture enables data to flow through different internal FPGA elements with non-contentious access. Multiple internal data buses and DMA engines provide for a flexible platform that supports various combinations of source/destination pathways. Intra-processor queue mechanisms and PowerPC functions involving message passing and command & control are abstracted from primary data paths to minimize overhead and enable maximum total bandwidth.

Fully leveraging the capabilities of the Xilinx Virtex-4 FX140 family of FPGA’s, CoSine utilizes high speed Rocket I/O Multi-Gigabit transceivers for connectivity to serial switch fabrics such as the four full-duplex 3.125 Gb/s LVDS lines required by Serial RapidIO and PCI-Express.

Multi-Ported Memory Controllers versus Bus-Translation Bridges
Although CoSine has multiple high speed internal data buses between logical blocks, bridging through large multi-ported memory controllers is the highest performance solution for transferring data between different bus protocols in real time.

Instead of relying on bus-translation bridges that have limited FIFO’s, bridge disconnects, inefficient pre-fetching, and retires that result in latency and throughput penalties, CoSine supports multiple paths with concurrent access to its large Primary DDR array.  This provides seamless, transparent access between endpoints residing on different bus topologies and results in maximum total bandwidth.

Fixed-Point Operations

Data movement is a critical component to efficient processing of real time sensor streams.  With this is mind, CoSine’s architecture and internal connectivity are logically optimized for input data to flow through pipelined, parallelized operations in the UPL block, with results DMA’d to conventional DSP compute nodes (Altivec® PowerPC’s, TI C6x, etc.) for intelligent processing.  These logic structures in the CoSine UPL block can involve repetitive fixed point functions such as:

- FFT, IFFT                            - Digital filters & Down Conversion

- FIR filters                           - IQ Demodulation

- Data reduction                    - Pulse Compression

- Convolution

In addition to these front end DSP functions, other CoSine operations can involve backend processing such as image construction, compression, time tagging, and parsing of output data as part of a data acquisition system.

CoSine makes DSP’s more efficient

Signal processors spend a significant portion of time and resources moving data, shuffling it in preparation for manipulation.  Through the use of a large, multi-ported memory buffer tightly integrated with the UPL block and a corner turning DMA engine, CoSine significantly reduces this inefficiency for downstream DSP’s.  This unique combination enables downstream DSP’s to spend a higher percentage of time and resources on intelligent data manipulation, reducing overhead and system complexity.

By having a proportionately large front end memory system, input data can be rate buffered for downstream DSP’s.  The larger memory array tightly coupled to the input stream and FPGA processing engine also has the ability to efficiently service multiple conventional downstream DSP compute nodes.

CoSine links:

Applications

Device Interfaces

Development Kit and Board Station

CoSine on Othello™ VxS VITA 41 and VITA 46/48