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UPL Block
The User Programmable Logic (UPL) block enables users to develop
their own custom logic inside of CoSine. Located in the primary
data path with multiple points of simultaneous access, the UPL is
intended for functions such as FFT’s, FIR filters, data reduction,
convolution, down conversion and IQ Demodulation.
Multiple points of
high speed access to the UPL block ensure efficient data movement
while providing flexibility and reducing complexity. UPL logic has
direct control and accessibility over its local DMA engine, the QDR
II SRAM memory controller, and other associated interfaces that were
designed so that they could be easily integrated with other custom
functionality. Control, status, and interrupt paths are supported
between the UPL and other CoSine interfaces.
Fixed Timing
Constraints
Providing user’s the power of a true System-On-Chip, along with a
platform that gives them the ability to focus on their application
specific logic has been a key consideration in CoSine’s architecture
and development. Towards this end, with the exception of the UPL
block and its associated QDR controller and local DMA engine, the
CoSine bitstream is supplied with isolated clock domains and fixed
timing constraints. This strategy gives the flexibility and freedom
to program custom logic in the UPL block but not spend several weeks
balancing timing constraints and resource utilization for other
elements of the device.
The UPL has
several fixed, predefined interfaces to the rest of the CoSine
device which are defined in the VHDL wrapper file. Outside of the
UPL related blocks, the timing of the rest of the device has been
pre-established by area and location constraints for critical
portions based on the reference 1024 FFT UPL block. Extensive
floorplanning has been used to maximize overall utilization of the
Virtex-II Pro 2VP70 and ensure that timing is maintained when new
custom logic is introduced into the UPL. After integration is
complete, the user is then responsible for ensuring that the UPL
block and associated elements meet system timing requirements as
established by the CoSine user constraint file (.ucf file).
CoSine
Development Kit and MM-333D Board Station
Programming in the UPL Block requires purchasing the CoSine
Development Kit. Included in this package are the CoSine bitstream,
MM-333D Board Station, Developer’s Manual, VHDL UPL wrapper, and
Demo Program. Also included is a full suite of diagnostic C test
code that verifies correctness of FFT’d data.
In addition to
hand coded VHDL, the CoSine UPL block supports the use of MATLAB’s
Simulink and Xilinx’s System Generator.
Xilinx’s ChipScope
is supported for in-chip logic debugging. A host of other
associated features and capabilities are described in more detail in
the CoSine Development Kit.
Developer’s
Manual
The primary focus of the Developer’s Manual is
centered around descriptions of the UPL VHDL wrapper and information
required to develop VHDL in the UPL block.
It describes all
interfaces from the UPL block to the rest of the CoSine FPGA
bitstream and the QDR II SRAM memory controller. It illustrates
different UPL resource usages and implementations, such as with
regards FIFO’s and memory‑mapped accesses.
Also included are
descriptions of DMA operations that pipe data through the UPL block
and illustrations of how signals are used for data transfer.
Software interfaces are documented on how the embedded PowerPC’s can
be used to initialize, command, and control the UPL.
Demo Program
The UPL block is intended for customer application specific logic,
but to demonstrate CoSine’s capabilities and the UPL block’s
functional interfaces a demo program is provided that implements an
off-the-shelf Xilinx 1024 Radix-4 streaming FFT as an example
application.
This program
demonstrates full system capabilities, including configuration and
control by the PowerPC with DMA transfers from external interfaces.
The QDR II SRAM memory, internal Block RAMs, FIFO’s, and multiplexed
accesses are also utilized to buffer the 1024 FFT data.
UPL DMA
The UPL DMA serves a critical function because it reduces the number
of data movements in the system. Using a single DMA operation or
DMA chain to move and process the data instead of transfers to and
from additional external processor nodes, the UPL DMA utilizes a
proven interface to move data between the UPL block and its
associated QDR II SRAM. This allows developers to focus on the UPL
implementation instead of the logic required to perform the data
movements.
QDR II SRAM
Interfacing to the UPL block, CoSine includes a dedicated QDR
controller with 32MB of QDR II SRAM memory. Especially applicable
to fixed point operations, QDR offers the unique characteristic of
simultaneous read/write operations.
For many DSP
functions, available block RAM within the Virtex-II Pro 2VP70 is
sufficient. But for requirements that exceed the available internal
block RAM, the 32MB of QDR is a high speed, powerful resource for
multiply/accumulate functions and rapid parallel processing.
The memory can be
used by the UPL for FIFOs, corner‑turning memory, coefficient
storage, or other, implementation dependent uses.
An optional QDR
parity module is offered outside of the QDR controller for greater
flexibility. |
