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Serial RapidIO Module
RapidIO is a packet switched interconnect targeted toward memory
mapped distributed memory systems and subsystems. The serial RapidIO
interface on CoSine uses four full duplex 3.125 Gb/sec lines
operating in parallel. Full duplex operation is achieved by using
separate differential transmit and differential receive pins and
traces. The serial RapidIO physical and protocol layers use 10 bits
to transmit 8 bits of information and a packet size of 276 bytes to
transmit 256 bytes of data. The remainder of this maximum sized
packet is used, similarly to Ethernet, to identify the sender,
recipient, CRCs, and protocol information. This results in a maximum
data rate of 1.16 GB/sec simultaneously in each direction. The
RapidIO protocol includes error recovery mechanisms for packet
retry, stomp, link request/response, and CRC.
In addition to the Xilinx LogiCORE Serial RapidIO
interface, significant backend logic has been implemented in
CoSine’s Serial RapidIO module. This backend logic contains a
RapidIO control/status module that generates and consumes RapidIO
packets as it processes requests from the transport layer and
generates appropriate responses. This module also generates RapidIO
transport layer requests based on commands from the Serial RapidIO
corner turning DMA engine.
Utilizing the Xilinx Virtex-II Pro’s MGT Rocket
I/O SerDes, the LogiCORE Serial RapidIO x4 interface provides the
external interface for the module. It utilizes the LogiCORE physical
layer core and logical (I/O) and transport layer interface core. The
physical layer implements the physical and link layers for a four
lane (x4) serial endpoint RapidIO interface. The transport layer
core implements the transport layer, which provides an interface for
sending and receiving RapidIO request and response packets and a
management module for processing maintenance packets. A buffer
module is utilized to interconnect these two core modules and
provide the buffering/prioritization for the RapidIO interface
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